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1/20 october 2002 n complete interface between lnb and i2ctm bus n built-in dc/dc controller for single 12v supply operation n accurate built-in 22khz tone oscillator n suits widely accepted standards n fast oscillator start-up facilitates diseqctm encoding n built-in 22khz tone detector supports bi-directional diseqctm n loop-through function for slave operation n lnb short circuit protection and diagnostic n cable length digital compensation n internal over temperature protection n esd rating 4kv on power input-output pins description intended for analog and digital satellite stb receivers/sattv, sets/pc cards, the lnbp21 is a monolithic voltage regulator and interface ic, assembled in so-20 and powerso-20, specifically designed to provide the power and the 13/18v, 22khz tone signalling to the lnb lnbp21 lnbp supply and control ic with step-up converter and i 2 c interface enable i select preregul.+ u.v.lockout +p.on res. feedback step-up controller v select linear post-reg +modulator +protections 22khz oscill. vup lt1 out sda scl dsqin vcc diagnostics i2c interf. tone detector dsqout lt2 detin lnbp21 byp gate sense extm addr schematic diagram so-20 powerso-20
lnbp21 2/20 downconverter in the antenna or to the multiswitch box. in this application field, it offers a complete solution with extremely low component count, low power dissipation together with simple design and i 2 ctm standard interfac-ing. this ic has a built in dc/dc step-up controller that, from a single supply source ranging from 8 to 15v, generates the voltages that let the linear post-regulator to work at a minimum dissipated power. an undervoltage lockout circuit will disable the whole circuit when the supplied v cc drops below a fixed threshold (6.7v typically). the internal 22khz tone generator is factory trimmed in accordance to the standards, and can be controlled either by the i 2 c tm interface or by a dedicated pin (dsqin) that allows immediate diseqc tm data encoding (*). all the functions of this ic are controlled via i 2 c tm bus by writing 6 bits on the system register (sr, 8 bits) . the same register can be read back, and two bits will report the diagnostic status. when the ic is put in stand-by (en bit low), the power blocks are disabled and the loop-through switch between lt1 and lt2 pins is closed, thus leaving all lnb powering and control functions to the master receiver (**). when the regulator blocks are active (en bit high), the output can be logic controlled to be 13 or 18 v (typ.) by mean of the vsel bit (voltage select) for remote controlling of non-diseqc lnbs. additionally, it is possible to increment by 1v (typ.) the selected voltage value to compensate for the excess voltage drop along the coaxial cable (llc bit high). in order to minimise the power dissipation, the output voltage of the internal step-up converter is adjusted to allow the linear regulator to work at minimum dropout. another bit of the sr is addressed to the remote control of non-diseqc lnbs: the ten (tone enable) bit. when it is set to high, a continuous 22khz tone is generated regardless of the dsqin pin logic status. the ten bit must besetlowwhenthedsqinpinisusedfor diseqc tm encoding. the fully bi-directional diseqc tm interfacing is completed by the built-in 22khz tone detector. its input pin (detin) must be ac coupled to the diseqc tm bus, and the extractedpwkdataareavailableonthe dsqout pin (*). in order to improve design flexibility and to allow implementation of newcoming lnb remote control standards, an analogic modulation input pin is available (extm). an appropriate dc blocking capaci-tor must be used to couple the modulating signal source to the extm pin. when external modulation is not used, the relevant pin can be left open. the current limitation block has two thresholds that can be selected by the i sel bitofthesr;the lower threshold is between 400 and 550ma (i sel =high), while the higher threshold is between 500 and 650ma (i sel =low). the current protection block is soa type. this limits the short circuit current (isc) typically at 200ma with i sel =high and at 300ma with i sel =low when the output port is connected to ground. it is possible to set the short circuit current protection either statically (simple current clamp) or dy-namically by the pcl bit of the sr; when the pcl (pulsed current limiting) bit is set to low, the overcurrent protection circuit works dynamically: as soon as an overload is detected, the output is shut-down for a time t off , typically 900ms. simultaneously the olf bit of the system register is set to high. after this time has elapsed, the output is resumed for a time t on =1/ 10t off (typ.). at the end of t on , if the overload is still detected, the protection circuit will cycle again through toff and ton. at the end of a full ton in which no overload is detected, normal operation is resumed and the olf bit is reset to low. typical ton+toff time is 990ms and it is determined by an internal timer. this dynamic operation can greatly reduce the power dissipation in short circuit condition, still ensuring excellent power-on start up in most conditions (**) . however, there could be some cases in which an highly capacitive load on the output may cause a difficult start-up when the dynamic protection is chosen. this can be solved by initiating any power start-up in static mode (pcl=high) and then switching to the dynamic mode (pcl=low) after a chosen amount of time. when in static mode, the olf bit goes high when the current clamp limit is reached and returns low when the overload condition is cleared. this ic is also protected against overheating: when the junction temperature exceeds 150c (typ.), the step-up converter and the linear regulator are shut off, the loop-trough switch is opened, and the otf bit of the sr is set to high. normal operation is resumed and the otf bit is reset to low when the junction is cooled down to 140c (typ.). (*): external components are needed to comply to bi-directional diseqc tm bus hardware require-ments. full compliance of the whole appli- cation to diseqc tm specifications is not implied by the use of this ic. (**): the current limitation circuit has no effect on the loop-through switch. when en bit is low, the current flowing from lt1 to lt2 must be externally limited.
lnbp21 3/20 ordering codes absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these condition is not implied. thermal data pin configuaration (top view) type so-20 (tube) so-20 (tape & reel) powerso-20 (tube) powerso-20 (tape & reel) lnbp21 lnbp21d2 lnbp21d2-tr LNBP21PD LNBP21PD-tr symbol parameter value unit v cc dc input voltage 16 v v up dc input voltage 25 v v lt1 ,v lt2 dc input voltage 20 v i o output current internally limited ma v o dc output pin voltage -0.3 to 22 v v i logic input voltage (sda, scl, dsqin) -0.3 to 7 v v detin detector input signal amplitude 2 v pp v oh logic high output voltage (dsqout) 7v i lt bypass switch on current 900 ma v lt bypass switch off voltage 20 v i gate gate current 400 ma v sense current sense voltage -0.3 to 1 v v address address pin voltage -0.3 to 7 v t stg storage temperature range -40 to +150 c t op operating junction temperature range -40 to +125 c symbol parameter so-20 powerso-20 unit r thj-case thermal resistance junction-case 15 2 c/w powerso-20 so-20
lnbp21 4/20 table a: pin configurations symbol name function pin number vs package so-20 powerso-20 v cc supply input 8v to 15v supply. a 220f bypass capacitor to gnd with a 470nf (ceramic) in parallel is recommended 19 18 gate exrernal switch gate external mos switch gate connection of the step-up converter 17 17 sense current sense input current sense comparator input. connected to current sensing resistor 14 16 v up step-up voltage input of the linear post-regulator. the voltage on this pin is monitored by internal step-ut controller to keep a minimum dropout across the linear pass transistor 20 19 out output port output of the linear post regulator modulator to the lnb. see truth table for voltage selections. 12 sda serial data bidirectional data from/to i 2 c bus. 11 1 2 scl serial clock clock from i 2 cbus. 12 13 dsqin diseqc input when the ten bit of the system register is low, this pin will accept the diseqc code from the main m controller. the lnbp21 will use this code to modulate the internally generated 22khz carrier. set to gnd thi pin if not used. 13 14 detin detector in 22khz tone detector input. must be ac coupled to the disecq bus. 99 dsqout diseqc output open collector output of the tone detector to the main m controller for disecq data decoding. it is low when tone is detected. 10 15 extm extrernal modulator external modulation input. need dc decoupling to the ac source. if not used, can be left open. 45 gnd ground circuit ground. it is internally connected to the die frame for heat dissipation. 5,6,15,16 1,10,11,20 byp bypass capacitor needed for internal preregulator filtering 8 8 lt1 loop through switch in standby mode the power switch between lt1 and lt2 is closed. max allowed current is 900ma. this pin can be left open if loopthrough function is not needed. 34 lt2 loop through switch same as above 2 3 addr address setting four i 2 c bus addresses available by setting the address pin level voltage 77
lnbp21 5/20 typical application circuit (*) set to gnd if not used (**) filter to be used according to eutelsat reccomendation to implement the diseqc tm 2.x, not needed if bidirectional diseqc tm 2.x is not implemented (see diseqc implementation note) (***) ic2 is a st fettky, sts4dnfs30l, that includes both the schottky diode and the n-channel mos-fet, needed for the dc/dc converter, in a so-8 package. it can be replaced by a schottky diode (stps2l3a or similar) and a n-channel mos-fet (stn4nf03l or similar) i 2 c bus interface data transmission from main p to the lnbp21 and viceversa takes place through the 2 wires i2c bus interface, consisting of the two lines sda and scl (pull-up resistors to positive supply voltage must be externally connected). data validity as shown in fig. 1, the data on the sda line must be stable during the high period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. start and stop conditions as shown in fig.2 a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high transition of the sda line while scl is high. a stop condi-tions must be sent before each start condition. byte format every byte transferred to the sda line must contain 8 bits. each byte must be followed by an ac-knowledge bit. the msb is transferred first. acknowledge the master (p) puts a resistive high level on the sda line during the acknowledge clock pulse (see fig. 3). the peripheral (lnbp21) that acknowledges has to pull-down (low) the sda line during the acknowledge clock pulse, so that the sda line is stable low during this clock pulse. the peripheral which has been addressed has to generate an acknowledge after the reception of each byte, other-wise the sda line remains at the high level during the ninth clock pulse time. in this case the master transmitter can generate the stop information in order to abort the transfer. the lnbp21 won't gen-erate the acknowledge if the vcc supply is below the undervoltage lockout threshold (6.7v typ.). transmission without acknowledge avoiding to detect the acknowledge of the lnbp21, the p can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. this approach of course is less protected from misworking and decreases the noise immunity. 270h 15 ohm see note 2 lnbp21 vup gate vin 12v l1=22h sense c2 220f vcc lt1 master stb vo lt2 detin (note 1) c8 10nf to lnb sda scl dsqout dsqin(note 1) address byp c5 470nf gnd 0 lnbp21 6/20 figure 1 : data validity on the i 2 cbus figure 2 : timing diagram on i 2 cbus figure 3 : acknowledge on i 2 cbus
lnbp21 7/20 lnbp1 software description interface protocol the interface protocol comprises: - a start condition (s) - a chip address byte = hex 10 / 11 (the lsb bit determines read(=1)/write(=0) transmission) - a sequence of data (1 byte + acknowledge) - a stop condition (p) ack= acknowledge s= start p= stop r/w= read/write system register (sr, 1 byte) r,w= read and write bit r= read-only bit all bits reset to 0 at power-on transmitted data (i 2 cbuswritemode) when the r/w bit in the chip address is set to 0, the main p can write on the system register (sr) of the lnbp21 via i 2 c bus. only 6 bits out of the 8 available can be written by the p, since the re-maining 2 are left to the diagnostic flags, and are read-only. x= don't care. values are typical unless otherwise specified received data (i 2 c bus read mode) the lnbp21 can provide to the master a copy of the system register information via i2c bus in read mode. the read mode is master activated by sending the chip address with r/w bit set to 1. at the following master generated clocks bits, the lnbp21 issues a byte on the sda data bus line (msb transmitted first). at the ninth clock bit the mcu master can: - acknowledge the reception, starting in this way the transmission of another byte from the lnbp21; chip address data msb lsb msb lsb s0001000r/wack ackp msb lsb r, w r, w r, w r, w r, w r, w r r pcl isel ten llc vsel en otf olf pcl isel ten llc vsel en otf olf function 001xx v out =13v, v up =16v loopthrough switch open 011xx v out =18v, v up =21v loopthrough switch open 101xx v out =14v, v up =17v loopthrough switch open 111xx v out =19v, v up =22v loopthrough switch open 0 1 x x 22khz tone is controlled by dsqin pin 1 1 x x 22khz tone is on, dsqin pin disabled 01xx i out(min) =500ma, i out(max) =650ma i sc =300ma 11xx i out(min) =400ma, i out(max) =550ma i sc =300ma 0 1 x x pulsed (dynamic) current limiting is selected 1 1 x x static current limiting is selected x x x x x 0 x x power blocks disabled, loopthrough switch closed
lnbp21 8/20 - no acknowledge, stopping the read mode communication. while the whole register is read back by the p, only the two read-only bits olf and otf convey di-agnostic informations about the lnbp21. values are typical unless otherwise specified power-on i2c interface reset thei2cinterfacebuiltinthelnbp21is automatically reset at power-on. as long as the vcc stays be-low the undervoltage lockout threshold (6.7v typ.), the interface will not respond to any i2c com-mand and the system register (sr) is initialised to all zeroes, thus keeping the power blocks disabled. once the vcc rises above 7.3v, the i2c interface becomes operative and the sr can be configured by the main p. this is due to about 500mv of hysteresis provided in the uvl threshold to avoid false retriggering of the power-on reset circuit. diseqctm implementation the lnbp21 helps the system designer to implement the bi-directional (2.x) diseqc protocol by al-lowing an easy pwk modulation/ demodulation of the 22khz carrier. the pwk data are exchanged between the lnbp21 and the main p using logic levels that are compatible with both 3.3 and 5v mi-crocontrollers. this data exchange is made through two dedicated pins, dsqin and dsqout, in or-der to maintain the timing relationships between the pwk data and the pwk modulation as accurate as possible. these two pins should be directly connected to two i/o pins of the p, thus leaving to the resident firmware the task of encoding and decoding the pwk data in accordance to the diseqc pro-tocol. full compliance of the system to the specification is thus not implied by the bare use of the lnbp21. the system designer should also take in consideration the bus hardware requirements, that include the source impedance of the master transmitter measured at 22khz. to limit the attenuation at car-rier frequency, this impedance has to be 15ohm at 22khz, dropping to zero ohm at dc to allow the power flow towards the peripherals. this can be simply accomplished by the lr termination put on the out pin of the lnbp, as shown in the typical application circuit on page 5. unidirectional (1.x) diseqc and non-diseqc systems normally don't need this termination, and the out pin can be directly connected to the lnb supply port of the tuner. there is also no need of tone decoding, thus, it is recommended to connect the detin and dsqout pins to ground to avoid emi. address pin connecting this pin to gnd the chip i2c interface address is 0001000, but, it is possible to choice among 4 different addresses simply setting this pin at 4 fixed voltage levels (see table on page 10). electrical characteristics for lnbp series (t j = 0 to 85c, en=1, llc=0, ten=0, isel=0, pcl=0, dsqin=0, v in =12v, i out =50ma, unless otherwise specified. see software description section for i 2 c access to the system register) pcl isel ten llc vsel en otf olf function these bits are read exactly the same as they were left after last write operation 0 t j <140c, normal operation 1 t j >150c, power block disabled, loothrough switch open 0 i out i omax , overload protection triggered symbol parameter test conditions min. typ. max. unit v in supply voltage i o = 500 ma ten=vsel=llc=1 8 15 v v lt1 lt1 input voltage 20 v i in supply current i o = 0ma ten=vsel=llc=1 en=1 20 40 ma en=0 2.55ma v o output voltage i o = 500 ma vsel=1 llc=0 17.3 18 18.7 v llc=1 19 v
lnbp21 9/20 v o output voltage i o = 500 ma vsel=0 llc=0 12.5 13 13.5 v llc=1 14 v d v o line regulation v in1 =15 to 18v vsel=0 5 40 mv vsel=1 5 60 mv d v o load regulation vsel=0 or 1 i out = 50 to 500ma 200 mv i max output current limiting isel=1 400 550 ma isel=0 500 650 ma i sc output short circuit current isel=1 200 ma isel=0 300 ma t off dynamic overload protection off time pcl=0 output shorted 900 ms t on dynamic overload protection on time pcl=0 output shorted t off /10 ms f tone tone frequency ten=1 20 22 24 khz a tone tone amplitude ten=1 0.55 0.72 0.9 vpp d tone tone duty cycle ten=1 40 50 60 % t r ,t f tone rise and fall time ten=1 5 10 15 m s g extm external modulation gain d v out / d v extm , f = 10hz to 40khz 6 v extm external modulation input voltage ac coupling 400 mvpp z extm external modulation impedance f = 10hz to 50khz 260 w v lt loopthrough switch voltage drop (lt1 to lt2) en=0, i lt =300ma, v mi =12 or 19v 0.35 0.6 v f sw dc/dc converter switch frequency 220 khz f detin tone detector frequency capture range 0.4vpp sinewave 18 24 khz v detin tone detector input amplitude f in =22khz sinewave 0.2 1.5 vpp z detin tone detector input impedance 150 k w v ol overload flag pin logic low tone present i ol =2ma 0.3 0.5 v i oz overload flag pin off state leakage current tone absent v oh =6v 10 m a v il dsqin input pin logic low 0.8 v v ih dsqin input pin logic high 2v i ih dsqin pins input current v ih =5v 15 m a i obk output backward current en=0 v obk = 18v -4 -10 ma t shdn temperature shutdown threshold 150 c d t shdn temperature shutdown hysteresis 15 c symbol parameter test conditions min. typ. max. unit
lnbp21 10/20 gate and sense electrical characteristics (t j = 0 to 85c, v in =12v) i 2 c electrical characteristics (t j =0to85c,v in =12v) address pin characteristics (t j = 0 to 85c, v in =12v) test circuit symbol parameter test conditions min. typ. max. unit r dson-l gate low r dson i gate =-100ma 4.5 w r dson-h gate low r dson i gate =100ma 4.5 w v sense current limit sense voltage 200 mv symbol parameter test conditions min. typ. max. unit v il low level input voltage sda, scl 0.8 v v ih high level input voltage sda, scl 2 v i ih input current sda, scl, v in = 0.4 to 4.5v -10 10 m a v il dsqin input pin logic low sda (open drain), i ol = 6ma 0.6 v f max maximum clock frequency scl 500 khz symbol parameter test conditions min. typ. max. unit v addr-1 "0001000" addr pin voltage 0 0.7 v v addr-2 "0001001" addr pin voltage 1.3 1.7 v v addr-3 "0001010" addr pin voltage 2.3 2.7 v v addr-4 "0001011" addr pin voltage 3.3 5 v gate vup lt1 out vcc extm dsqout 10nf lt2 detin 10nf scope probe v mi, v obk lnbp21 470nf byp i o ,i obk a vin a i in a i lt v v out load 20f v a i oz /i ol ol v oh /i ol sda scl scl sda { from i 2 c master dsqin pulse gen. v extm, v detin sense stn4nf03l r sc 0.1 w w w w 220f 470nf stps2l30a 220f 470nf l1=22h address v 1n4001 v v lt 10nf
lnbp21 11/20 typical characteristics (unless otherwise specified t j =25c) figure 4 : output voltage vs temperature figure 5 : output voltage vs temperature figure 6 : line regulation vs temperature figure 7 : line regulation vs temperature figure 8 : load regulation vs temperature figure 9 : load regulation vs temperature
lnbp21 12/20 figure 10 : supply current vs temperature figure 11 : supply current vs temperature figure 12 : dynamic overload protection on time vs temperature figure 13 : dynamic overload protection off time vs temperature figure 14 : output current limiting vs temperature figure 15 : output current limiting vs temperature
lnbp21 13/20 figure 16 : tone frequency vs temperature figure 17 : tone amplitude vs temperature figure 18 : tone duty cicle vs temperature figure 19 : tone rise time vs temperature figure 20 : tone fall time vs temperature figure 21 : loopthrought switch drop voltage vs temperature
lnbp21 14/20 figure 22 : loopthrought switch drop voltage vs temperature figure 23 : loopthrought switch drop voltage vs loopthrought current figure 24 : loopthrought switch drop voltage vs loopthrought current figure 25 : dsqout pin logic low vs temperature figure 26 : undervoltage lockout threshold vs temperature figure 27 : output backward current vs temperature
lnbp21 15/20 figure 28 : dc/dc converter efficiency vs temperature figure 29 : current limit sense vs temperature figure 30 : 22khz tone figure 31 : dsqin tone enable transient response figure 32 : dsqin tone enable transient response figure 33 : dsqin tone disable transient response v cc = 12v , i o =5 0 m a , en = ten = 1 v cc = 12v , i o =5 0 m a , en = 1 , ten = 0 v cc = 12v , i o =5 0 m a , en = 1 , ten = 0 v cc = 12v , i o =5 0 m a , en = 1 , ten = 0
lnbp21 16/20 figure 34 : output voltage transient response from 13v to 18v figure 35 : output voltage transient response from 13v to 18v termal design notes during normal operation, this device dissipates some power. at maximum rated output current (500ma), the voltage drop on the linear regulator lead to a total dissipated power that is of about 1.7w. the heat generated requires a suitable heatsink to keep the junction temperature below the overtemperature protection threshold. assuming a 40c temperature inside the set-top-box case, the total rthj-amb has to be less than 50c/w. while this can be easily achieved using a through-hole power package that can be attached to a small heatsink or to the metallic frame of the receiver, a surface mount power package must rely on pcb solutions whose thermal efficiency is often limited. the simplest solution is to use a large, con-tinuous copper area of the gnd layer to dissipate the heat coming from the ic body. the so-20 package of this ic has 4 gnd pins that are not just intended for electrical gnd connec-tion, but also to provide a low thermal resistance path between the silicon chip and the pcb heatsink. given an rthj-c equal to 15c/w, a maximum of 35c/w are left to the pcb heatsink. this figure is achieved if a minimum of 25cm2 copper area is placed just below the ic body. this area can be the inner gnd layer of a multi-layer pcb, or, in a dual layer pcb, an unbroken gnd area even on the opposite side where the ic is placed. in both cases, the thermal path between the ic gnd pins and the dissipating copper area must exhibit a low thermal resistance. in figure 4 , it is shown a suggested layout for the so-20 package with a dual layer pcb, where the ic ground pins and the square dissipating area are thermally connected through 32 vias holes, filled by solder. this arrangement, when l=50mm, achieves an rthc-a of about 25c/w. different layouts are possible, too. basic principles, however, suggest to keep the ic and its ground pins approximately in the middle of the dissipating area; to provide as many vias as possible;tode-signadissipatingareahavinga shape as square as possible and not interrupted by other copper traces. due to presence of an exposed pad connected to gnd below the ic body, the powerso-20 package has a rthj-c much lower than the so-20, only 2c/w. as a result, much lower copper area must be provided to dissipate the same power and minimum of 12cm2 copper area is enough, see figure 5. v cc = 12v , i o =5 0 m a , vsel = f rom 0 to 1 , en = 1 v cc = 12v , i o =5 0 m a , vsel = f rom 1 to 0 , en = 1
lnbp21 17/20 figure 36 : so-20 suggested pcb heatsink layout figure 37 : powerso-20 suggested pcb heatsink layout
lnbp21 18/20 dim. mm. inch min. typ max. min. typ. max. a 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 c 0.5 0.020 c1 45? (typ.) d 12.60 13.00 0.496 0.512 e 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 f 7.40 7.60 0.291 0.300 l 0.50 1.27 0.020 0.050 m 0.75 0.029 s ? (max.) so-20 mechanical data po13l 8
lnbp21 19/20 dim. mm. inch min. typ max. min. typ. max. a 3.60 0.1417 a1 0.10 0.30 0.0039 0.0118 a2 3.30 0.1299 a3 0 0.10 0 0.0039 b 0.40 0.53 0.0157 0.0209 c 0.23 0.32 0.0090 0.0013 d (1) 15.80 16.00 0.6220 0.630 e 13.90 14.50 0.5472 0.5710 e 1.27 0.0500 e3 11.43 0.4500 e1 (1) 10.90 11.10 0.4291 0.4370 e2 2.90 0.1141 g 0 0.10 0.0000 0.0039 h 1.10 0.0433 l 0.80 1.10 0.0314 0.0433 n0?10? s0? 8?0? 8? t 10.0 0.3937 powerso-20 mechanical data 0056635 e a2 a e a1 pso20mec detail a t d 110 11 20 e1 e2 h x 45? detail a lea d slug a3 s gage plan e 0.35 l detail b r detail b (coplanarity) gc -c- seating plane e3 b c n n (1) d and e1 do not include mold flash or protusions - mold flash or protusions shall not exceed 0.15mm (0.00 6 ) 1
lnbp21 20/20 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no res ponsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devi ces or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com

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